The present invention is related to systems and methods for processing information, and more particularly to systems and methods for reducing latency in determining a sampling clock used for data processing.
Data transfer systems typically include a receiver that converts an analog input into a stream of digital samples representing the analog input. For example, in a hard disk drive system, digital information is converted to an analog signal that is stored as a magnetic signal on a storage medium. The magnetic information is later sensed and converted back to an analog signal using a read circuit. The received analog signal is converted back to digital information representing the digital information originally provided to the storage medium. As another example, a wireless communication system involves a transmitter that receives digital information, and converts it to an analog signal that is transmitted. The analog signal is received and converted back to the original digital information that was originally prepared for transmission.
Turning to FIG. 1, a prior art system 100 for converting a received analog signal into corresponding digital information is depicted. System 100 includes an analog to digital converter that converts an analog input 105 into a series of digital sample values that are provided to a filter 120 that is synchronized to a sample clock 125. Filter 125 provides a real output 130 that is provided to a Viterbi detector 140. Viterbi detector 140 is synchronized to sample clock 125, and performs a detection process that yields an ideal output 145. Ideal output 145 and real output 130 are both provided to a comparator 150 that yields an error value 155. Error value 155 is provided to a clock adjustment circuit 160. Clock adjustment circuit 160 receives a reference clock 165 and is operable to provide sample clock 125. Thus, sample clock 125 is adjusted based upon a combination of real output 130 and ideal output 145.
Proper operation of the timing loop in a decoding system is critical for the overall performance since it determines how accurately the data is originally sampled. In system 100, the frequency and phase of sample clock 125 are derived from the information contained in analog input 105. The process of determining the phase and/or adjusting the phase of sample clock 125 relies on the output of Viterbi detector 140. Thus, there is a substantial latency involved in determining the proper phase of sample clock 125. Such latency negatively impacts any ability to determine the appropriate frequency of sample clock 125. For this reason, various algorithms have been proposed to perform zero phase start where the phase of sample clock 125 is determined as quickly as possible. The required calculations are often, however, very complex and prone to error since there can be a significant amount of noise present in the system.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for reducing latency in the determination of clock phase in a data processing system.